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Data Sheet
Table 10. SDP, CP Pixel Input/Output Pin Map (P40 to P20)
P ixe l Port Pins P[40:31], P[29:20]
ADV7403
Processor Mode
Format
40 39 38 37 36 35 34 33 32 31 29
28
27
26
25
24
23
22
21 20
SDP
SDP
SDP
SDP
Video out, 8-bit, 4:2:2
Video out, 10-bit, 4:2:2
Video out, 16-bit, 4:2:2
Video out, 20-bit, 4:2:2
SDP
SDP
SM-SDP
CP
CP
CP
CP
CP
CP
CP
Video out, 24-bit, 4:4:4
Video out, 30-bit, 4:4:4
Digital tuner input[1]
8-bit, 4:2:2, DDR
10-bit, 4:2:2, DDR
12-bit, 4:4:4, RGB DDR
Video out, 16-bit, 4:2:2
Video out, 20-bit, 4:2:2
Video out, 24-bit, 4:4:4
input
Video out, 30-bit, 4:4:4
input
DCVBS[9:0] IN
Cr[7:0] OUT
Cr[9:0] OUT
CHC[7:0] OUT (for example, R[7:0])
CHC[9:0] OUT (for example, R[9:0])
SM-CP
HDMI receiver support,
G[7:0] IN
R[7:6] IN
B[7:0] IN
R[3:2] IN
24-bit, 4:4:4 input
SM-CP
HDMI receiver support,
CHA[7:0] IN (for example, Y[7:0])
CHB/C[7:0] IN (for example, Cr/Cb[7:0])
16-bit, pass through
SM-CP
HDMI receiver support,
CHA[9:0] IN (for example, Y[9:0])
CHB/C[9:0] IN (for example, Cr/Cb[9:0])
20-bit, pass through
Rev. B | Page 17 of 20
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